VHCG

Introduction

VHCG is a Viterbi HDL Codes Generator. It can generate the Verilog HDL codes of
some kinds of viterbi decoders by setting some parameters. It is synthesiable and passed FPGA test.
If you have any question, please email to me Jhonson.zhu@gmail.com

Features


Graphics

The GUI version of VHCG:

VHCG_GUI.png

The CMD version:

perl perl/Oracle.pl -POLYS "91 121 101 91" -B 1 -V 1 -RAW 10 -OSR 5 -DBN 2 -SYNCRAM 1

Download

You can download VHCG from the sourceforge download page.
This latest version is version1.3

Here is some examples generated by VHCG

Document

Specification.pdf

Tools

There are some tools, which maybe you will use for VHCG.

ActivePerl    TK lib    Icarus for windows   

Q/A

There are some discussion about VHCG on opencores.org
The first one is including a short help for vhcg, written by moti.

Q1.
Hi Wasay,

I used the VHCG to generate an IP with the same parameters (and I'm
almost sure with the same generator polynoms). I received a request
just a few days ago requesting the same help.
I copied the section about the generator parameters I used to generate
the core. I know ... motilito 2008/01


Q2.
Hi Edgarbges,

I posted an answer to a similar question regarding the VHCG a few
months ago... motilito 2008/11

Link

VHCG at opencores.org    Google     



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